Digital coded security system



June 2, 1970 J. l. MIKA DIGITAL CODED SECURITY SYSTEM 3 Sheets-Sheet 1Filed NOV. 25, 1966 INVENTOR. swab/1M ATTORNEYS June 2, 1970 J. MIKADIGITAL CODED SECURITY SYSTEM 3 Sheets-Sheet 2 Filed NOV. 25, 1966INVENTOR. JOHN 1. MIKA gimhw. 787

ATTORNEYS.

BM mQW O XOm JOQFZOO 2 June 2, 1970 J. MIKA DIGITAL CODED SECURITYSYSTEM .3 Sheets-Sheet s Filed Nov. 25, 1966 I7 -IB INVENTOR. JOHN I BYM1,

ATTORNEYS.

United States Patent US. Cl. 23561.7 1 Claim ABSTRACT OF THE DISCLOSUREThis is a security system for permitting access to secured premises.Satisfaction of a code card provides energy for a plurality of pushbutton switchable lines. Input lines and output lines on a patch boardprovide for selection of a switch code involving energizing of aselected few of the output lines in sequence. The selected lines areindividually applied to the stages of a register of cascaded binarydevices. In response to successive energization of the selected lines,in accordance with the switch code, the binary devices are successivelyset and the final binary device activates a qualifying device permittingaccess for a limited time. The disclosure includes an OR gate which sogates false signals on the non-selected output lines of the patch boardas to cause reset. The disclosure features AND circuit means for causingresetting upon sensing coincidence between a reset state of any binarydevice, and an out-of-sequence signal applied over one of the selectedlines to any of the succeeding binary devices.

The present invention provides an improved digital coded security systemof the type employed to control entry into secured areas, vaults, safesor similar places requiring protection.

The principal object of the invention is to provide a novel securitysystem which employs the'combination of a key code, built into a card inthe possession of an authorized user, and a coded combination of manualoperations, such as the depression of a sequence of push buttons, i.e.,a switch code. These codes set up electrical circuitry which controlsthe operation of a door latch or like entry-permitting mechanism.

Another object of the invention is to provide a security system of suchfool-proof character that access is negated if a non-coded button isdepressed or if a coded button is depressed out of its proper sequenceor if the key code is not satisfied.

Another object of the invention is to provide an improved securitysystem in which the switch code may readily be changed, the systemaffording a large number of code selections.

It is also an object of the present invention to provide simplifiedcircuitry for limiting the access-permitting operations to apredetermined period.

For a better understanding of the invention, together with other andfurther objects, advantages and capabili ties thereof, reference is madeto the following description of the accompanying drawings, in which:

FIG. 1 is a circuit diagram of a complete security system in accordancewith the invention (with the exception of the FIG. 2 circuitry). TheFIG. 1 elements are in box .11;

FIG. 2 is a schematic diagram of the circuitry in the control box 10 andalso the patch board in box 11;

FIG. 3 is a perspective view of the control box and the cabinetcontaining the processing circuitry;

FIGS. 4 and 5 are top plan and side views of the assembly of switcheswhich are actuated by the key card; and

FIG. 6 is a top plan view of the key card.

The digital code security system in accordance with Patented June 2,1970 the invention prevents unauthorized personnel (those not possessingthe key code or those not knowing the switch code) from gaining entry oraccess to a protected area. Only an autorized person, in possession of akey code or card code and with knowledge of the switch code, can gainaccess to the secured area and then only by performing the requisiteoperations.

The system is packaged in two containers 10 and 11 (FIG. 3). The encoderor control box 10 houses the devices on which the operator performsmanual operations. For convenience this container 10 is located at theentrance port.

The other container 11 houses the circuitry (FIG. 1) which causes to beoperated the latching and unlatching mechanism through which access tothe secured area is obtained or barred, as the case may be. Thecontainer 11 (FIG. 3) is preferably installed inside the protected area.The container 11 also houses the mechanism uti lized to change theswitch code. The two boxes 10 and 11 are interconnected by anappropriate cable 12.

A system in accordance with the invention utilizes two codes, a key codeand a switch code. The key or card code is provided by a magneticallycoated portable card 13 (FIG. 6), which is made of plastic material, iscarried around by the operator and has imbedded in it a ferro-magneticelement '14, the position of which is codesignificant. The control box10 is formed with an opening 15 into which the card is inserted. If theelement 14 on the card registers positionally with a magnet .16 (FIG. 5)then reed switches 17 and 18 are operated in the manner described andsupply power to and permit the operation of the FIG. 1 system.

A valid key code supplies power to the FIG. 1 circuitry and unlocks thedigital circuitry. A valid switch code sets up the circuitry so that theentrance to the secured area is unlocked for a predetermined time. Thenthe FIG. 1 circuitry is reset. Entry is permitted only duringapredetermined interval.

As previously indicated, the control box 10 contains the card insertionaperture 15 and the card detection magnet which actuates the reedswitches 17 and 18. Additionally, the twelve push-button switches 21-32(of which four are used in any one of the selected switch codes) arealso mounted on the box 10-. The container 11 houses all of the elementsin FIG. 1, excepting cable 12, which are not included in the control box10. The container 11 houses the processing circuitry and the patch boardand plug-in devices which are employed in the predetermination of thedesired switch code, i.e., the push buttons depressed and the sequenceaccording to which they are to be depressed. In order to gain access tothe secured area the following sequence of events must occur:

First, the authorized person or operator inserts the code card 13 in theslot 15. The placement of the ferromagnetic insert 14 on the card issuch that the card is compatible to the particular security system andregisters with the magnet 16. Parenthetically, it will be understoodthat the magnet 16 and the magnetic element 14 may be placed in anydesired position width-wise or length-wise, the point being that theyregister when compatible.

Note that with the code card out, both of the normally open reedswitches 17 and 18 (FIGS. 4 and 5) are actuated and held in the closedposition by the permanent magnet 16 that is located under them. When thecode card '13 is inserted, reed switches 17 and 18 will open up as thecard slides into place, due to the magnetic shielding elfect of theinsert 16. If the card is a correct card for the particular box, reedswitch 18 will stay open but reed switch 17 will again close when thecard is fully inserted into its slot 15. This operation of the reedswitches is caused by the unique location of the piece of magneticmaterial 14 in the code card. If the card is compatible with the system,then the switch 18 will stay open but the switch 17 will again closewhen the card is fully inserted into the slot. The opening of switch 18allows the switch code to be read into the processing circuitry, becauseit ungroiunds a line 19 which would otherwise prevent the code frombeing read into the first binary device described below.

Second, the proper switch code is satisfied by depressing the switchbuttons in the required sequence. The twelve available push-buttonswitches are numbered 21- 32, and they are used four at a time, forexample 21-24 in the particular embodiment shown. That is, the switchcode is selected by putting the plugs for wires 41-44 into the jacks forwires 58-61. The plugs for wires 45-52 are arranged as shown in FIG. 2.

Third, the electrical processing circuit generates an output command online 33 which causes to be energized a port-unlatching solenoid 34. Theperiod of the unlatching is approximately eight seconds. After thiseight-second period the system is automatically reset.

In order to provide satisfactory security, a two-part code philosophy isemployed. The first part of the twopart code is the simple code card 13which must be inserted; the second part of the code is thefour-out-oftwelve push-button switch arrangement which is activated inthe proper sequence. The chance of a successful opening by anunauthorized person who has obtained the code card is one out of thecombination of twelve things taken four at a time. This figure is(12)(l1)(10) (9): 11,880. The number of possible chances is at leastdoubled by the use of the code card; hence, the security againstunauthorized entry is at least 1 out of 23,760 trials.

A word is in order at this time about some additional security featuresof this system. One of these is provided because the processingcircuitry is located inside of locked box -11 and within the securedarea. This tends to prevent tampering. The wiring from the control boxis housed in a protective conduit 12. Additionally, the impedance ofeach of the input wires from the control box to the processing circuitryis matched, and this fact renders compromise more diflicult.

Referring now specifically to FIG. 2, it will be seen that all read-inpower is supplied through switch 17, which switch is connected by line36 to the regulator 37 included in the power supply, which regulatorsupplies 12 volts on line 38. When reed switch 17 is closed, 12 volts isaccordingly available on bus bar 39. When power is available on bus bar39, energy is supplied to the inputs of all of the switchable circuitsincluding the push buttons 21-32. Parenthetically, in the event that apiece of ferro-magnetic material is inserted in slot in lieu of the codecard 13, the switches 17 and 118 will open and remain open, therebykeeping bus bar 39 deenergized and preventing eifective use of thepush-button switches. On the other hand, after a correct code card 13has been inserted, then bus bar 39 is energized and the operator canactivate the system by correctly operating the four selected push-buttonswitches. Depression of any of these switches causes a 12 volt signal toappear on its respective output line. These lines are numbered 41through 52. Only the lines 41-44 are used to provide the switch codeinput to the processing box in the following description of operationhere given.

Included in the box 11 is a code-selecting patch board 53 whichcomprises simply twelve jacks and plugs. The output of the patch boardgoes to the processing circuitry.

The purposes of the processing circuitry are these: first, to set up inresponse to the proper switch code; second, to provide an output tounlock the door when the correct codes have been provided; third, togenerate a reset signal and return to a passive state whenever the'wrong button is depressed or whenever a correct code button isdepressed in the wrong sequence; and fourth, to generate an automaticresetting signal in any event after a sufficient time for entry oraccess has elapsed.

The principal wiring diagram of the system is shown in FIGS. 1, 2. Inthe particular embodiment here presented there are twelve push-buttonswitches 21-32 in the control box .10 and the ultimate operation, i.e.,the opening of an entrance door, etc., is performed only when fourflip-flops 54-57 are set. In other words, the preferred embodiment isconcerned with permutations of twelve things taken four at a time.

Now the elements which do the taking are four flip flops, variouslyreferred to as binary devices or binaries, these being numbered 54, 55,56 and 57. These four binaries will make transitions from zero or resetstate to a one or set state as they do the taking, that is, providedthat the lines 58, 59, 60 and 61 are activated in sequence. These linesare activated or energized in sequence by closing the push-buttonswitches so as to accomplish that sequence. To that end the lines 41,42, 43 and 44 are run into a patch board for connection by plugs andjacks to lines 5'8-61. This patch board will accept any combination orpermutation of the four push button switches. Those push-button switches25-32 which are not used for the security code and which should not bepressed may, however, be pressed and are employed to reset the binarydevices. In other words, if one of these push-button switches isdepressed then any of the binary devices which is in the one state isreset back to zero, thus effectively preventing code discovery by trialand error methods.

Parenthetically, the mode of accomplishment of the last mentionedfunction is quite simple and will 'be described at this time. Theswitches 25-32 are plugged in on the patch board 53 to jacks which areconnected by wires 62-69 to diodes -77 and all of these diodes(collectively referred to as error detection gate) are so poled and theswitches so connected to the bus bar 39 that in the event of thedepression of any one of the switches 25-32 a positive potential isimpressed on line 79, which potential is used for resetting purposes aswill later appear.

It is a condition of the setting of binary circuit 54 that the ground heremoved from diode by opening switch 18, also that push button 21 bepressed. The corresponding conditions for changing the binaries 55, '56and 57 to the one state are as follows: (a) as to binary 55that pushbutton 23 be pressed and that the preceding binary device 54 be in theone state; (b) as to binary 56-that push button 23 be pressed anr thatthe preceding binary device 55 be in the one state; and (c) as to binary57-that push button 24 be pressed and that the preceding binary device56 be in the one State.

It has been seen that the input circuit 81 to the first binary device 54is activated only in response to two conditions. The first of theseconditions, as has been stated, is that line 58 is energized and thesecond of these conditions is that the ground connection be removed byswitch 18 from diode 80. Accordingly, an and gate 82 constitutes theread-in circuit for bistable device 54 and diode 83 is the read-indiode. The diode 80 functions as an inhibiting input until switch 18opens. Each of the other binary devices 55, 56 and 57 is provided withan input circuit such as 84 which comprises the output of an and gatesuch as 85 comprising two diodes, such as 88 and 89, poled to pass onlycoincident positive levels or rather a positive pulse on top of apositive level. Only one of the gates 85, 86, and 87 is described indetail because the operation of all is the same. The sequential binaries54- 57 and the activating inputs provided by AND gates 82, 85, 86 and 87are collectively a conventional subcombination.

Parenthetically, resistors 90, 91, 92 and 93 are individually connectedbetween the inputs of the read-in diodes and ground. The gates at theinputs to the binary devices 55, 56 and 57 are numbered 85, 86 and 87.Each of the read-in diodes (say 89) of gates '82 and 85-87 is connectedto that line (say 59) which when energized by depression of a pushbutton (say 22) is intended to activate the associated binary device(say 55). The other diode (say 88) of each gate, is connected to anoutput circuit of the preceding bistable device (say 54), with theexception of the first binary device 54, and as to that one, the diodeis connected to the reed switch 18.

Thus the first binary device 54 changes from the zero to the one statewhen line 58 is energized after the ground is removed from diode 80. Thesecond binary device 55 changes to the one state on condition that theline 59 iS energized when the binary device 54 is in its one state.Binary device 56 changes to the one state on the condition that line 60is energized when the second binary device is in its one state. Binarydevice 57 changes to the one state if line 61 is energized while device56 is in the one state. In other words each binary device responds tological and information to change from a zero to a one state and thefour elements of the switch code, being potentials on lines 58, 59, 60and 61, have to be presented in sequence before they are taken.

It has already been pointed out that the diodes 70-77 constituteerror-detection gates which cause the four binary devices to be reset tothe zero state in the event of an inadvertent or purposeful depressionof a pushbutton switch not employed in the desired code. M respecifically, the OR gate having an output at 79 comprises a firstplurality of diodes 70-77 individually connected to the false signallines 62-69 for causing resetting of all the binary devices in the eventof a signal on one of the false signal lines. To give an example of afalse signal, depression of button 32 would put a false signal on line69.

Further in accordance with the invention there are provided sequenceerror-detection gate circuits which assure that the bistable devices canbe operated only in the proper sequence, 54, 55, 56, 57. All of the gatecircuits 94-99 are normally conductive and when any of them becomesnonconductive the 12 volt potential on line 160 is applied to the resetline 79. The proper sequence must be maintained.

This is accomplished by a combination of six and gates numbered 94, 95,96, 97, 98, and 99, having outputs connected to diodes 100, 101, 102,103, 104, and 105. Each one of these gates has two diodes of which oneis connected to the read-in line of a binary device and of which theother is connected to an output line of a preceding binary device. Thelogical an is satisfied on the condition that an effort is made toactivate a binary device when a preceding binary device is in its zerostate. Each of and gates 94-99 functions to sense any coincidence thatthere may be with respect to the reset state of an associated binarydevice and an out-ofsequence signal on any of the true signal linesappurtenant to any of the succeeding binary devices. This undesiredcontingency can occur in six different ways: Attempts to set the second,third and fourth binary devices before the first, or to set the third orfourth binary device before the second, or to set the fourth binarybefore the third. Accordingly, six and gates 94-99 are provided, one foreach undesired contingency. That is, if in the wrong sequence an effortis made to activate binary device 57 before binary device 56 isactivated then gate 99 will cause resetting, passing a positive outputthrough diode 105 to line 79. If in the wrong sequence an effort is madeto activate binary device 57 before binary device 55 is activated thengate 98 will cause resetting, passing a positive output through diodei104 to line 79. If in the wrong sequence an effort is made to activatebinary device 57 before binary device 54 is activated then gate 96 willcause resetting, passing a positive output through diode 102 to line 79.If in the wrong sequence an effort is made to activate binary device 56before binary device 55 is activated then gate 97 will cause resetting,passing a positive output through diode 103 to line 79. If in the wrongsequence an effort is made to activate binary device 56 before binarydevice 54 is activated then gate 95 will cause resetting, passing apositive output through diode 101 to line 79. If in the wrong sequencean effort is made to activate binary device 55 before binary device 54is activated then gate 94 will cause resetting, passing a positiveoutput through diode to line 79.

The binary devices are generally similar and only one is discussed asrepresentative. It is a simple NPN transistor binary quite similar tothat shown in Fig. 10-7 at p. 371 of the text entitled Pulse, Digitaland Switching Wave Forms, Millman and Taub, McGraw-Hill Book Company,1965, New York. A positive-going pulse supplied at 81 changes thisbinary from the zero to the one state. When the binary 54 is in the zerostate a positive potential of approximately 12 volts is available at itscollector output 106 which is coupled to the sequence error-detectiongates 94, 95 and 96. On the other hand, when the binary is in the onestate a positive potential of approximately 12 volts is available in itsoutput 107 which is coupled to the next binary 55. Thus each binaryeither tells the sequence error-detection gates that it has not yetchanged from zero to one or it goes to a one state to enable the nextbinary device.

When binary device 57 assumes its one state it transmits a negativelevel via line 33 to a transistorized relay driving system whichcomprises transistors 121 and 122. The emitter of transistor 121 isconnected to the positive supply line 123. Its base is connected viaresistor 124 to line 33 and the junction of diode 1125 and resistor 126.A collector load resistor 127 is connected between its collector andground. The collector is coupled by resistor 128 to the base of agrounded emitter transistor 122, the collector of which is in seriescircuit with the coil 34 of a solenoid, with resistor 129 and with thepositive supply line 38, the solenoid being shunted by diode 130 forpurposes of transient suppression. The solenoid actuates an armature 35closing a circuit which is arranged to control an entrance door releaseor unlatching mechanism. Such unlatching mechanisms and releases andtheir input circuits are well known to those of skill in the art andneed not be described in detail herein. The group of elements activatedby line 33, i.e., 121, 122, 124, 127, 128, 129, 130, 34 and 35 iscollectively referred to as a qualifying device. These elementscollectively operate to qualify the person seeking admission and topermit access for a period of time.

The overall circuit functions as follows: When a correct code sequenceis generated, the first code switch 21 output sets the first flip flop54. An output level from this flip flop enables one side 88 of atwo-side and gate 85 connected to the input of the next flip flop 55 anddisables the error-detection gates 94, 95, 96 associated with first fiipflop. Operation of the next correct code switch 22 on the control box 10enables the other side of this previously mentioned two-side gate 85.The output now provided through this two-side gate sets the second flipflop 55 and disables its error-detection gate circuits 97-98. Thisprocess continues on 60 and 61 for the next two input pulses. On thefourth pulse the last flip flop 57 of the series is set, and an outputpulse is coupled into both the relay driver 121, etc., and a monostablemultivibrator delay circuit I131. The closure of the relay contacts 35supplies a voltage which is then applied to a door unlatching device.

The circuit 131 is a monostable device and its function is to establisha predetermined access interval during which the solenoid 34 isenergized. In this monostable configuration a positive triggering signalon line 132 induces a transition from the stable state to thequasistable state. The diode 142 carries a positive pulse to the base oftransistor 135 but prevents negative voltages from reaching thetransistor. The monostable circuit 131 remains in its quasi-stable statefor a time which is very long in comparison with transition betweenstates. Eventually, however, it automatically returns from thequasistable state to its stable state.

The monostable device herein shown comprises a first 7 NPN transistor133 which has its collector coupled by resistor 134 to the base of asecond NPN transistor 135. The emitters are grounded and the collectorsof the transistors are provided with collector load resistors 136 and137 connected to the 12 volt line 138. Transistor 135 has a baseresistor 139 coupled between its base and ground.

The trigger circuit input 132 to the monostable device 131 originates atthe collector of the output transistor 140 of the last binary device 57and it passes, via capacitor 141, to the junction of a diode 142 andresistor 143, the latter two elements being connected between the baseof transistor 135 and ground. An input signal to this monostable device131 causes it to assume its quasistable state. After a predeterminedtime it returns to its stable state and applies to the base oftransistor 144 via series capacitor 145 and series resistor 146 andshunt resistor 147, a signal which causes resetting to occur. Themonostable device comprising the transistors 133 and 135 and allelements grouped between the input 132 and the output 169 arecollectively referred to as a timer or timing means. This group ofelements provides a signal that insures that the binary devices will bereset and the function of the qualifying device terminated, therebylimiting access to a short period of time.

The description now proceeds to the details of the arrangement by whichthe four binary devices are reset. All of the diodes 70-77 and 100-105and 159 are connected to a common line 79 which constitutes the baseinput of a transistor 148. This is the reset driver transistor. Anemitter resistor 149 is connected between its emitter and ground and abase resistor 150 is connected between its base and ground. Thetransistor is of an NPN type and is rendered conductive by a positivepotential applied to its base. The collector of 148 goes to the supplyline 38. Between line 38 and ground is disposed a time constant circuitcomprising a capacitor 151 and a resistor 152. A pair of diodes 153 and154 are connected in a chain with opposite polarity between the junctionof 151, 152 and the emitter of 148. The junction of the cathodes ofthese diodes is connected to the principal reset line 155, which in turnis coupled to the bases of the righthand transistors of each of binarydevices 54-57. For example, the reset line 155 is coupled to the base oftransistor 140 by the series combination of resistor 156 and diode 157.A positive pulse appearing on line 155 causes all of the bistabledevices to be reset.

A positive pulse may be caused to occur on line 155 in either of twoways. Whenever the wrong push button is depressed or a proper pushbutton (such as one of 21-24) is depressed out of the proper sequence, apositive potential appears on line 79 and this renders conductive thetransistor 148 and it applies, via diode 153, a positive pulse to thereset line 155. The second mode in which the pulse can be applied toline 155 is associated with the first application of power (i.e., theturning on of the entire system) to line 38, whereupon a chargingcurrent flows through the time constant circuit 152, 151, applying apositive pulse, via diode 154, to line 155, thus assuring that wheneverpower is turned on all of the binary devices will be reset. The elementsincluding transistor 148, having an input at line 79 and an output atrest line 155, constitute a reset driver, essentially an amplifier orrepeater, i.e., effectively a part of the coupling between the principalOR gate and the common reset circuitry for the binary devices.

Reference is now made to the double inverter circuitry comprisingtransistor 158 and transistor 144. The function of this circuitry is toreceive a pulse via 145, to amplify it and to apply it with properpolarity to line 79 via diode 159 at the termination of thepredetermined access time. The transistors 158 and 144 have theiremitters connected together and to ground, the base of transistor 158being connected to the collector of transistor 144 and the collector ofthe transistor 158 being connected to diode 159. These transistors havecollector load resistors 190 and 161 and the base of the inputtransistor is provided with a base resistor 147. The elements 145, 146and 147 constitute a differentiating circuit. The elements having aninput at resistor 146 and an output connected to diode 154 constituteessentially an amplifier or repeater, in the coupling between the timerand input 159 of the OR gates.

The regulated rectifier system here employed is conventional andcomprises a transformer having a primary connected to the supply lineand a secondary connected to a full wave rectifier network which feedsinto a filter comprising series resistor 111, shunt capacitor 112,series filter choke 113, shunt capacitor 114, shunt resistor 115, and aregulator circuit 37 which includes transistor 116. The collector oftransistor 116 is connected to the high potential terminal of resisior115. A resistor 117 is inserted between its base and collector and aZener stabilizing diode 118 between its base and ground. An emitterresistor 119 is connected between the emitter and ground and the 12 voltsupply line 38 originates at this emitter; that line is connected viaresistor to line 36 and the eed switch 17 to supply power to bus bar 39.

A word is now in order about the operation of the monostable circuit131. At the time that the last binary device 57 is set it applies to thebase of transistor a positive pulse, via line 132, capacitor 141, andpositive pulse steering diode 142, which renders transistor 135conductive, its collector simultaneously dropping in voltage andproducing the leading edge of a square Wave pulse. This pulse is ameasure of the time delay between the setting of the last binary 57 andthe resetting of all the binaries. The trailing edge of this square wavepulse is differentiated and the positive portion of the difierentiatedwave form is applied, via differentiating circuit 145, 146, 147 to thebase of transistor 144 of the double inverter circuit which comprisestransistors 158 and 144. The output of this double inverter is appliedvia diode 159 to line 79 to activate the reset driver to cause all ofthe binary devices to be reset. Thus all binary devices areautomatically reset after a predetermined time delay following thesetting of the last binary 57. This action limits the access time, i.e.,the energization of solenoid 34, to a predetermined interval, whichinterval is substantially equal to the length of the square wave outputoccurring at the collector of transistor 135, which output isrepresentative of the quasi-stable state of the monostable 131.

As transistor 135 becomes conductive, at the beginning of theqausi-stable state aforesaid, transistor 133 is cut off. During thestable state of the monostable, capacitor 165 had charged up, via thecircuit comprising line 138, resistor 166, capacitor 165, the baseemitter circuit of transistor 133, and ground, but when the transistor133 was cut otf, at the beginning of the quasi-stable state, then thecapacitor slowly discharges through its time constant discharge circuitwhich includes resistors 168 and 166. At the end of the discharge ofcapacitor 165, transistor 133 becomes conductive and transistor 135 iscut off and the monostable resumes its stable state. As the transistor135 is cut off its collector rises in voltage, terminating the squarewave output, and it is this rise which is differentiated as statedaforesaid. As the rise occurs the diode 167 isolates the time constantdischarge circuit of capacitor 165 from the collector, the diode thenbeing cut off.

The three diodes numbered 170, 171 and 172 prevent equalizing currentsfrom being exchanged among shunt filter capacitors 173, 174 and 175 inthe voltage supply network, as to which the element 38 is the bus bar.

Thus it will be seen that the invention comprises, in a security system,the combination of a normally disabled switch-coded system (FIGS. 1-2,generally) and means including two complementary elements 14, 16 (FIGS.5-6) for enabling the switch-coded subsystem only in response to aproper relative placement of those elements by a carrier of one of them,14. The normally disabled switch-coded subsystem comprises all of theparts of the system with the exception of the card 14 and the switchingdevices 17, 18 which are illustrated in FIGS. 4 and 5. The twocomplementary elements are the ferromagnetic insert in the card 13 andthe magnet 16 with which the element 14 registers. One of thesecomplementary elements is carried by the authorized employee. Only inresponse to the proper relative placement of the elements 14 and 16 bythis employee is the subsystem enabled by reason of the closure ofswitch 17 (FIG. 2), which supplies power, and the opening of switch 18,removing the disabling ground connection from the input 80 of the firstbinary device 54.

The switch-coded subsystem comprises the larger number of individuallymanually operable switch elements 21- 32 (FIG. 2), each adapted toenergize lines, and a smaller number of true signal lines 58-61 (FIGS.1-2) adapted to be energized in sequence and to be coupled by the patchboard 53 (FIG. 2) to selected ones of the switch elements (2124 in theembodiment herein shown) in accordance with a selected permutationrepresentative of a switch code (the permutation here being21-22-23-24). The subsystem also includes a plurality of false signallines 62-69 (FIGS. 1-2) and means in the patch board 53 for coupling thenon-selected manually operable switch elements 2532 to the false signallines 62-69. A plurality of binary devices 54-57 (FIG. 1) are cascadedto be activated in sequence as the signal lines 5861 are energized bymanipulation of the selected manually operable switch elements 2124.

The subsystem further included error-detecting means 70-77 (FIG. 1) incircuit with the false signal lines 62- 69 for detecting operation ofany one of the non-selected manually operable switch elements 25-32. Thesystem further includes means (i.e., the reset driver 148, etc.)responsive to the error-detecting means for resetting the binarydevices.

An additional feature of the subsystem is the sequence error-detectingmeans which comprises a plurality of gates 9499 (FIG. 1), each havingtwo inputs, the gates being associated with all of the binary devicesexcept the first. In any one of the gates, such as 99, one of the inputsis connected to the signal line (such as 61) for the binary device (suchas 57) sought to be set and the other of the inputs is connected to anoutput of a proceeding binary device, for example device 56. Each ofsuch gates functions in such a manner that the binary device sought tobe set (for example 57) cannot be set unless all of the preceding binarydevices have been set. The inputs of all of the binary devices compriseindividual and gates. Each of these and gates, for example gate 85, hastwo inputs. One input (for example 89) is connected to the appropriatesignal line (59) and (except in the case of the gate 82 for the firstbinary device) the other input is connected to the output (for example107) of the preceding binary device. In the case of gate 82, the otherinput is inhibited, except when switch 18 removes a ground from it. Inthe preferred embodiment of the invention all of the binary devices aretransistorized flip flops.

While there has been shown and described what is at present consideredto be the preferred embodiment of the invention, it will be understoodby those skilled in the art that various changes and modifications maybe made therein without departing from the scope of the invention asdefined by the appended claims.

I claim:

1. In a security system, a sequence detector comprismg:

a plurality of true signal lines adapted to be energized in sequence inaccordance with a selected code,

a plurality of false signal lines each adapted when energized to providea false signal,

a plurality of binary devices arranged in a series,

each binary device having a two-terminal AND circuit set input and areset input and a principal output,

each binary device except the last having a state-indicating output,

one terminal of each AND circuit set input being connected to itsrespective one of said true signal lines,

the other terminal of the first AND circuit set input being adapted tobe utilized for enabling and inhibiting as desired, the other terminalsof the remaining AND circuit set inputs being severally connected to theprincipal outputs of the respective preceding binary devices so that inresponse to energizing of said true signal lines in sequence the binarydevices are set in sequence,

a qualifying device coupled to the principal output of the last binarydevice and responsive to setting of the last binary device to performits qualifying function, and

error-detecting and sequence-error-detecting means responsive to a falsesignal or to a departure from the desired sequence of true signals forresetting all of said binary devices comprising:

an OR gate having an output coupled to all of said reset inputs,

said OR gate also having a first plurality of inputs individuallyconnected to said false signal lines so that resetting occurs inresponse to a false signal,

said error detecting means further comprising:

a plurality of two-terminal input AND gates in number corresponding tothe varieties of sequence errors that can occur,

the last-mentioned AND gates having output circuits and said OR gatehaving a second plurality of inputs individually connected to saidoutput circuits,

said last-mentioned AND gates being arranged in a sequence of groups,the groups being individually associated with all of the binary devicesexcepting the last, each group having collective input terminalconnections to the state-indicat ing output of the associated binarydevice and each group having input connections in severalty to the truesignal lines of the succeeding binary devices so that the groups arenormally enabled but are successively disabled as their associatedbinary devices are set and as true signals are received in propersequence, a logical AND not being satisfied, but so that in response tothe satisfaction of a logical AND by reason of an erroneous-sequencesignal delivered over a true signal line a logical AND will be satisfiedand a signal will be applied by one of said last-mentioned AND gatesthrough said OR gate to cause resetting of all binary devices to occur.

References Cited UNITED STATES PATENTS 7/1955 Whitehead. 9/1962 Crane.

9/1966 Ryno et al. 10/1968 Goldman 23561.7 X

T. J. SLOYAN, Assistant Examiner US. Cl. X.R.

